1. Field of the Invention
The present invention generally relates to a method for accessing a dual-port memory and more particularly, to a method wherein a data block programming procedure is performed upon the dual-port memory using status flags and check codes to determine the access sequence of the data.
2. Description of the Prior Art
In recent years, with the development in science and technology, the demand on the operating speed of central processing units (CPU's) increases. However, the operating speed-of a single CPU is far from satisfactory. Therefore, in many high-speed communication or computing systems, two CPU's are required to operate at the same time and data exchange is enabled between the two CPU's. Currently, the best approach is using a dual-port RAM (DPR) as an interface between two CPU's. Since the dual-port memory has a larger buffer capacity so that the each of the two CPU's regard the dual-port memory as its exclusive memory. Using such a dual-port memory, a simple access command enables data exchange between the two CPU's. Therefore, the dual-port memory has attracted tremendous attention.
Presently, the conventional dual-port memory has a very high buffer capacity and allows heavy traffic so as to randomly access the data in the memory. The dual-port memory enables two interface devices such as CPU's with two independent clock pulses to access the data in the dual-port memory. However, when the two CPU's access a memory on the same address to both write in or read from simultaneously, mistakes may occur and the CPU's may take a considerable long-time to handle. The long access time as well as wasted processor performance is a loss to the user.
Therefore, there exists a need in providing a method for accessing a dual-port memory by performing a data block programming procedure upon the dual-port memory and controlling the access sequence of the data so that the user can access the dual-port memory rapidly and correctly without interruption.